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So lets look at the load linked/store conditional instructions, which usually we call LL/SC instruction. We have them because atomic reading and writing in the same instruction even if we just do the write, if the read has tested positive for something. Is really bad for pipelining your processor. Lets look at the classical five stage pipeline where we fetch the code and read registers. Do the area operation. This is where compute the address for memory instructions. Then we have a memory axis stage and finally, we write the result to a register, if a register result exists in the instruction. Loads will be fetched, decoded and read the register, compute the address using that register, access memory to get the value from that address and then write the result to a register. An atomic read/write instruction, such as a swap, or test and set, or test and write, would compute the address and read registers. And then when it gets to the memory stage, it cannot do everything it needs to
