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hello everyone my name is Minh monk Im a technical marketing engineer for the high blings tool suite here at mentor Ill be the presenter for this webinar and the topic is about ensuring ddr4 electrical performance at intended data rate the goal here is that you want to know how much design margins you have with the data rate you plan to run the memory interface ad while considering all of the electrical factors before faba first Ill provide some insight into why just following the routing rules provided by either the controller or a memory vendor is not good enough in ddr4 designs nowadays running at high data rates secondly I will list some of the electrical considerations you need to make during the post layout verification process I will also explain in more details of some of these device related electrical factors such as why we need to consider D rating and V Rev training in ddr4 designs finally Ill demonstrate in hyperlynx how to optimize your design margins by performing tr