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in this screencast were going to be talking about how digital designs are physically implemented on programmable logic devices its all fair and while learning how to program these devices but we dont just want to treat them as black boxes that we can throw code up getting a low-level appreciation of whats going on inside the chip will in turn give you a better understanding of what your designs are actually compiling to and in turn make you a better engineer so as mentioned in a previous screencast both splds and CPLDs use and/or array logic to build digital designs why is it connected either by fuse or reprogrammable technology in order to build the soft expressions for each logic element this is a typical example of an array logic diagram we can see that we have two inputs a and B and theyre complements not a and not B which can be connected through the array of four and gates the result in terms of the and gates are connected to a single for input or gate a macro cell with thi
