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in this example we are using a CIC filter design model in converting it to an optimal fixed point implementation that is efficient in terms of resource utilization on a Xilinx vertex seven FPGA target here is the CIC filter model with two cascaded integrators and a down sampling block followed by a couple of cascaded comb filters we already have a fixed point implementation of the model using 32-bit while in data types the objective is to get a more efficient implementation that is stable and manages the big growth while meeting the tolerances are shown the data type optimization feature in fixed point designer automates the iteration process to choose all of the attributes of the optimal data type such as a word length the precision sinus etc for a system under design while meeting the behavioral constraints here in the script I have specified the system under design and the constraints as part of the optimization options once I let the optimization engine run you will notice the ite