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sb = store byte, sh = store halfword, sw = store word, sd = store doubleword. Adds value of t0 to the value of t1 and stores the sum into a0.
With RISC-V assembler, the operand order is destination/source except for stores. The store word ( sw ) instruction reads the lower 4 bytes of your source register and stores them into memory at the address given in the destination operand.
What is sp and how should it be used in the context of RISC-V functions? sp stands for stack pointer. We subtract from sp to create more space and add to free space. The stack is mainly used to save (and later restore) the value of registers that may be overwritten.
The RISC-V memory system is byte-addressable, meaning that each memory address refers to a particular byte in memory. The lb/sb instructions load/store the byte at the given address, thus misalignment is impossible.
RiscV binary instruction encoding Binary instruction encoding is the standard way to encode instructions for execution on a microprocessor. They are normally stored in an executable file, usually in the ELF format. Instructions can be either fixed width or variable width.
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In RISC-V, all arguments are passed via registers (and the stack if there arent enough registers). Refer to the calling convention document for the specifics, but at a high level, arguments are passed via a0 , a1 , a2 , and so on. When a function is complete, the return value is passed via a0 (and a1 if needed).
In addition to register operations, RISC-V instructions can use constant or immediate operands. These constants are called immediates because their values are immediately available from the instruction and do not require a register or memory access.
LD: The Load Double word (LD) instruction does the fetching of 64-bit value from memory and loads into the destination register (rd). SD: The Store Double word (SD) instruction does the copying of 64-bit value from register (rs2) and loads into the memory(rs1).

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