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So now, lets look at how do we form the offset index and tag in the address for set-associative caches? This is a two way set-associative cache that has four sets. When the processor produces an address, the least docHub bits that tell us where in the block we are, are still determined by the block size. The indexed bits are the ones that tell us which set are we talking about. So the number of index bits is determined by how many sets we have. In this case, we have four sets, so we need two index bits. The remaining bits are the tag. Like in a direct mapped cache, once we have placed the line in for example set zero, we know that everything that maps to set zero will have bits zero zero here, so we dont have to keep that in the tag. In set zero, we only need to make sure that what we now need, matches what we have in the uppermost bits, not in the indexed bits. Because the fact that were looking at set zero, means that we have already determined that these bits are zero zero,
