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hi Iamp;#39;m at Sperling Iamp;#39;m the editor-in-chief of semiconductor engineering Iamp;#39;m over at synopsis with Xiao Lin Chen is gonna talk today about formal sign-off shell and what are the problems with formal sign-off why is this an issue now when it wasnamp;#39;t maybe a couple years ago actually itamp;#39;s been lately sure though all along itamp;#39;s just that people didnamp;#39;t know how to address it in the way that you use for modifications and you sign off the you say youamp;#39;re done and then youamp;#39;re trying to sign off the design and the management would say so what have you done can you show me in the terms I can understand I understand whatamp;#39;s his simulation we have called a code coverage as well as functional coverage to measure the progress and completeness of your verification but in formal you set your properties are proven what does it actually mean so thatamp;#39;s why it prompted todayamp;#39;s todayamp;#39;s talk to talk about ho