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I would like to share with you our in-depth case study on optimizing our register map verification methodology. Our team at St Microelectronics compared Cadence Jasper CSR formal verification app and UVM with Cadence Xcelium on two register maps that we already verified with UVM. We looked at the time spent, functional and code coverage, and bugs found. First, we compare the time to set up the environment. Jasper CSR has a lot of automation. Our verification engineers dont have to write the assertions and also dont need any formal or SystemVerilog expertise. So, we were able to write the Jasper CSR attributes in only one day. In contrast, it took us nearly two weeks to first build the first UVM environment, as we must build many verification objects. We compared Jasper CSR to UVM on two different register maps. Lets look at one of these cases. Hi. This is Edoardo Bollea. For code coverage, Jasper stimulated all scenarios and was able to docHub and find