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hi everybody and welcome back to digital vsi design im dr adam thiemann of the annex labs at barilon university and today well be going over lecture 11 chip finishing and sign off our lecture today has two parts sign-off timing and chip finishing and sign-off well start with the first part sign-off timing or advanced concepts in static timing analysis so do you remember those pesky timing margins that we mentioned in the lecture about static timing analysis well if we look at the max delay and the min delay formulas we added this plus delta margin here to the data path and minus delta margin here to the data path it was some extra margin that we just added or subtracted to make our life harder and we discuss sku and jitter in fact skew we added here to these uh these formulas and jitter we also showed how it can be added or subtracted from from our formulas but is that all there is well if it was theres a good chance that all the cad engineers could retire theres a lot more so wh