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Lets understand what exactly this shadow page table is and what it is. In many architectures, for example, Intels X86 family, the CPU uses the page table for address translation. What that means is presented with the virtual address, The CPU gets to what? It first looks up the TLB to see if there is a match for the virtual page number contained in this virtual address. If there is a match, its a hit and it can translate this virtual address to the physical address. If it is a miss, CPU knows word in memory the page table data structure is kept by the operating system. And therefore what it does, it goes to the page table, which is in main memory, and retrieves the specific entry which will give it the translation from the virtual page number to the physical page number. And once it gets that, Itll stash it in the TLB, as well, and be able to generate the physical address that is specified by this particular virtual address. So thats the way the CPU does the translation in many arc