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hello everyone welcome to this short quiz on cmos vlsi design first question when did the channel of the mosfet formed when the channel in between source and drain is going to be formed is the question when the gate voltage is less than the threshold voltage now it is wrong when the gate voltage is greater than the threshold voltage yes this is the correct answer when the gate voltage is biased to zero volts no none of this so second one is the correct answer when the gate voltage is greater than vt you can observe here the channel will be created in between the source and drawing under the gate region this will be called as channel next question in the region where the cmos inverter exhibits gain the nmrs and p mass are biased in which region cmos inverter kind of arrangement we have done and we are expecting again means when we are connected in mass and p mass transistors are biased in saturation region we can expect the gain in saturation region it will be act as an amplifie
