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Have you ever wasted time for an EM simulation, only to find out your substrate stack-up was incorrect, causing you to throw away the results and redo the sim? Have you ever built a board to find out the trace impedance was incorrect simply due to a manual error? The need to verify trace impedance is crucial. As a PCB layout is generated, hundreds of signal Nets need to be routed, and it can be very easy to make a mistake. The impedance is going to depend on the following: The width and spacing of signal traces; whether or not the signal is missing a ground plane under the trace; incorrect Dk and Df; or even incorrect dielectric height. Missed issues lead to expensive redesigns and delays. For example, the engineering time it takes to design the board, and weeks for the board to be fabricated. Once it comes back, the time on the test bench to detect issues, only to then have to fix the board and resubmit for another fabrication. These delays to final product shipment can have a large i